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SP5659 2?ghz i 2 c bus low phase noise synthesiser preliminary information ds4296 issue 2. 2 m ay 2 00 2 ordering information SP5659/kg/mp1s (tubes) SP5659/kg/mp1t (tape and reel) (16-lead miniature plastic package) the SP5659 is a single chip frequency synthesiser designed for tuning systems up to 2?ghz. the rf preamplifier drives a divide-by two prescaler which can be disabled for applications up to 2ghz, allowing direct interfacing with the programmable divider, resulting in a step size equal to the comparison frequency. for applications up to 2?ghz the divide-by two is enabled to give a step size of twice the comparison frequency. the comparison frequency is obtained either from an on- chip crystal controlled oscillator or from an external source. the oscillator frequency f ref or the comparison frequency f comp may be switched to the ref/comp output; this feature is ideally suited to providing the reference frequency for a second synthesiser such as in a double conversion tuner (see fig. 5). the synthesiser is controlled via an i 2 c bus and responds to one of four programmable addresses which are selected by applying a specific voltage to the address input. this feature enables two or more synthesisers to be used in a system. the SP5659 contains four switching ports, p0-p3 and a 5-level adc, the output of which can be read via the i 2 c bus. the SP5659 also contains a varactor line disable and charge pump disable facility. features complete 2?ghz single chip system optimised for low phase noise selectable 42 prescaler selectable reference division ratio selectable reference/comparison frequency output selectable charge pump current varactor drive amplifier disable 5-level adc figure 1 ?pin connections ?top view variable i 2 c bus address for multi-tuner applications esd protection: 4kv, mil-std-883c, method 3015 (1) pin compatible with sp5658 (1) normal esd handling precautions should be observed. applications satellite tv high if cable tuning systems thermal data u jc = 41 c/w u ja = 111 c/w SP5659 1 2 3 4 5 6 7 8 mp16 16 15 14 13 12 11 10 9 charge pump crystal ref/comp address sda scl port p3 port p2 drive v ee rf input rf input v cc adc port p0 port p1
2 SP5659 preliminary information electrical characteristics t am b = - 20 c to + 80 c, v c c = + 45v to + 55v, reference frequency = 4mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. supply current, i cc rf input voltage rf input impedance rf input capacitance sda, scl input high voltage input low voltage input high current input low current leakage current input hysteresis sda output voltage charge pump output current output leakage current drive output current drive saturation voltage external reference input frequency external reference input amplitude crystal frequency crystal oscillator drive level recommended crystal series resistance crystal oscillator negative resistance ref/comp output voltage, enabled comparison frequency equivalent phase noise at phase detector rf division ratio reference division ratio p0, p1, p2, p3 sink current p0, p1, p2, p3 leakage current adc input voltage adc input current address input current high address input current low value 12 13,14 13,14 13,14 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5 1 1 16 16 2 2 2 2 2 3 7,8,9,10 11 11 4 4 50 3 0 1 2 200 4 35 10 400 240 480 10 68 58 50 2 08 + - 3 350 - 142 85 73 300 55 15 10 - 10 10 04 + - 10 350 200 20 500 16 200 2 131071 262142 10 6 10 1 - 05 min. max. ma ma mvrms mvrms mvrms ? pf v v a a a v v na ma mv mhz mvp-p mhz mvp-p ? ? mvp-p mhz dbc/hz ma a a ma ma v cc = 5v, pe = 1 (note 1) v cc = 5v, pe = 0 300mhz to 27ghz, pe = 1 (prescaler enabled) see fig. 4b 100mhz, pe = 1 (prescaler enabled) see fig. 4b 100mhz to 20ghz, pe = 0 (prescaler disabled) see fig. 4b see fig. 10 see fig. 10 input voltage = v cc input voltage = v ee v cc = v ee sink current = 3ma drive output disabled ac coupled sinewave ac coupled sinewave parallel resonant crystal (note 2) includes temperature and process tolerances ac coupled, re = 1, see note 3 see note 4 prescaler disabled, see table 1 prescaler enabled, see table 1 see table 1 v port = 07v v port = 132v see fig. 3 table 5 v cc > v input > v ee input voltage = v cc input voltage = v ee characteristic pin u nits conditions notes 1. maximum power consumption is 468mw with v cc = 55v and all ports off. 2. resistance specified is maximum under all conditions including start up. 3. if the ref/comp output is not used, it should be left open circuit or connected to v cc and disabled by setting re to logic 0. 4. 6khz loop bandwidth, phase comparator frequency 250khz. figure measured at 1khz offset dsb (within loop bandwidth).
3 SP5659 preliminary information supply voltage rf input voltage rf input dc offset port voltage total port current adc input dc offset ref/comp output dc offset charge pump dc offset drive dc offset crystal oscillator dc offset address dc offset sda, scl input voltage storage temperature junction temperature port in off state port in on state 12 13,14 13, 14 7-10 7-10 7-10 11 3 1 16 2 4 5, 6 absolute maximum ratings all voltages are referred to v ee at 0v max. min. 7 25 v c c + 03 14 6 50 v c c + 03 v c c + 03 v c c + 03 v c c + 03 v c c + 03 v c c + 03 6 + 150 + 150 value - 03 - 03 - 03 - 03 - 03 - 03 - 03 - 03 - 03 - 03 - 55 v v p-p v v v ma v v v v v v v c c parameter pin u nits conditions figure 2 - block diagram rf in address sda lock det 4 2/1 13 14 4 5 f comp charge pump crystal 2 osc 789 10 p3 p2 p1 p0 f pd 4 16/17 4-bit count 13-bit count programmable divider preamp 17-bit latch divide ratio 1-bit count pe phase comp i 2 c transceiver scl 6 charge pump 2-bit latch f pd /2 3-bit adc adc 11 3 power on detect 4-bit latch and port interface reference divider (see table 1) ref/comp 3 2-bit latch v cc v ee 15 c1, c0 f l f ref 5-bit latch and mode control logic (see table 6) disable drive 16 1 mode control p0 test control 12
4 SP5659 preliminary information comparison frequency 2mhz 1mhz 500khz 250khz 125khz 625khz 3125khz 15625khz 800khz 400khz 200khz 100khz 50khz 25khz 125khz functional description the SP5659 contains all the elements necessary C with the exception of a frequency reference, loop filter and external high voltage transistor C to control a varactor tuned local oscillator, so forming a complete pll frequency synthesised source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic which enables the generation of a loop with good phase noise performance. the block diagram is shown in fig. 2. the rf input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier interfaces with a 17-bit fully programmable divider via a 4 2 prescaler. for applications up to 20ghz rf input, the prescaler can be disabled, so eliminating the degradation in phase noise due to prescaler action. the divider is of mn 1 a architecture, where n = 16 or 17, the m counter is 13 bits and the a counter is 4 bits. the output of the programmable divider, f pd , is fed to the phase comparator where it is compared in phase and frequency domains with the comparison frequency f comp . this frequency is derived either from the on-chip crystal controlled oscillator or from an external reference source. in either case, the reference frequency f ref is divided down to the comparison frequency by the reference divider, which is programmable to one of 15 ratios as detailed in table 1. the output of the phase detector feeds a charge pump and loop amplifier section which, when used with an external high voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. by invoking the device test modes as described in fig. 3, table 6, the varactor drive output can be disabled, so switching the external transistor off. this allows an external voltage to be applied to the varactor line for tuner alignment purposes. similarly, the charge can also be disabled to a high impedance state. the programmable divider output f pd /2 can be switched to port p0 by programming the device into test mode as set out in table 6. programming the SP5659 is controlled by an i 2 c bus. data and clock are fed in on the sda and scl lines respectively, as defined by the i 2 c bus format. the synthesiser can either accept new data (write mode) or send data (read mode). the lsb of the address byte (r/w) sets the device into write mode if it is low and read mode if it is high. tables 1 and 2 in fig. 3 illustrate the format of the data. the device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an i 2 c bus system. table 4 in fig. 3 shows how the address is selected by applying a voltage to the address input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes are programmed. when the device is programmed into the read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the device generates an internal stop condition, which inhibits further reading. write mode (frequency synthesis) with reference to table 2, bytes 2 and 3 contain frequency information bits 2 14 to 2 0 inclusive. auxiliary frequency bits 2 16 and 2 15 are in byte 4. for most frequencies, only bytes 2 and 3 will be required. the remainder of byte 4 and byte 5 control the prescaler enable, reference divider ratio (see fig. 3), output ports and test modes (see table 6). after reception and acknowledgment of a valid address (byte 1), the first bit of the following byte determines whether the byte is interpreted as byte 2 (logic 0) or byte 4 (logic 1); the next data byte is then interpreted as byte 3 or byte 5, respectively. after two complete data bytes have been re- ceived, additional data bytes can be entered, where byte interpretation follows the same procedure without read- dressing the device. this procedure continues until a stop condition is received. the stop condition can be generated after any data byte; if, however, it occurs during a byte transmission then the previous data is retained. to facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 17 bits of the data have been received or after the generation of a stop condition. repeatedly sending bytes 2 and 3 only will not change the frequency. a frequency change when one of the following data sequences is sent to an addressed device: bytes 2, 3, 4, 5 bytes 4, 5, 2, 3 or when a stop condition follows valid data bytes thus: bytes 2, 3, 4, stop bytes 4, 5, 2, stop bytes 2, 3, stop bytes 2, stop bytes 4, stop it should be noted that the sp5569 must be addressed initially with both frequency and control byte data, since the control byte contains reference divider information which must be provided before a chosen frequency can be synthe- sised. this implies that after initial turn on, bytes 2, 3 and 4 must be sent followed by a stop condition as a minimum requirement. alternatively, bytes 2, 3, 4 and 5 must be sent if port information is also required. read mode when the device is in read mode the status byte read from the device on the sda line takes the form shown in fig. 3, table 3. bit 1 (por) is the power-on reset indicator and is set to a logic 1 if the v cc supply to the device has dropped below 3v (at 25?c), for example, when the device is initially turned on. the por is reset to 0 when the read sequence is table 1 - reference division ratios (4mhz external reference) r2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 r3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 r1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 r0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ratio 2 4 8 16 32 64 128 256 invalid 5 10 20 40 80 160 320
5 SP5659 preliminary information terminated by a stop command. when por is set high (at low v cc ), the programmed information is lost and the output ports are all set to high impedance. bit 2 (fl) indicates whether the device is phase locked, a logic 1 is present if the device is locked, and a logic 0 if the device is unlocked. bits 6, 7 and 8 (a2, a1, a0) combine to give the output of the adc. the adc can be used to feed afc information to the microprocessor via the i 2 c bus. additional programmable features prescaler enable the 4 2 prescaler is enabled by setting bit pe in byte 4 to a logic 1. a logic 0 disables the prescaler, directly passing the rf input to the 17-bit counter. bit pe is a static select only. charge pump current the charge pump current can be programmed by bits c1 and c0 in data byte 5, as defined in fig. 3, table 7. test mode the test modes are invoked by setting bit re to logic 0 and bit rts to logic 1 within the programming data and are selected by bits ts2, ts1 and ts0 as shown in fig. 3, table 6. when ts2, ts1 and ts0 are received, the device retains previously p2, p1 and p0 data. reference comparison frequency output the reference frequency f ref can be switched to the ref/ comp output (pin 3) by setting byte 5 bit re to logic 1 and bit rts to logic 0. the comparison frequency f comp can be switched to the ref/comp output by setting bit re to logic 1 and bit rts to logic 1. for re set to logic 0, the output is disabled and set to a high state. re and rts default to logic 1 during power-up, thus enabling f comp at the ref/comp out- put. figure 3 - data formats cont table 1 write data format (msb transmitted first) table 3 read data format 1 por 1 a0 byte 1 byte 2 address status byte 1 fl 0 x 0 x 0 x ma0 a1 ma1 a2 a a address input voltage level 0v to 01v cc open circuit 04v cc to 06v cc 09v cc to v cc table 4 adc levels ma0 0 1 0 1 ma1 0 0 1 1 table 5 address selection voltage on adc input 06v cc to v cc 045v cc to 06v cc 03v cc to 045v cc 015v cc to 03v cc 0v to 015v cc a1 0 1 1 0 0 a2 1 0 0 0 0 a0 0 1 0 1 0 a : acknowledge bit ma1, ma0 : variable address bits (see table 5) 2 16 -2 0 : programmable division ratio control bits pe : prescaler enable r3, r2, r1, r0 : reference division ratio select (see table 1) c1, c0 : charge pump current select (see table 7) re : reference oscillator output enable rts : ref/comp select when re = 1, test mode enable when re = 0 (see table 6) ts2, ts1, ts0 : test mode control bits (valid when re = 0 and rts = 1,see table 6) p0 : port p0 output state (always valid except when re = 0 and rts = 1 (see table 6) p3, p2, p1 : ports p2, p1 and p0 output states por : power on reset indicator fl : phase lock flag a2, a1, a0 : adc data (see table 4) x : dont care address programmable divider programmable divider control data control data ma0 2 9 2 1 r1 p1/ts1 1 2 14 2 6 2 16 c0 0 2 13 2 5 2 15 re 0 2 12 2 4 pe rts 0 2 11 2 3 r3 p3 msb 1 0 2 7 1 c1 ma1 2 10 2 2 r2 p2/ts2 lsb 0 2 8 2 0 r0 p0/ts0 byte 1 byte 2 byte 3 byte 4 byte 5 a a a a a
6 SP5659 preliminary information figure 3 - data formats (continued) table 6 - ref/comp output mode and test modes ts2 x x x x x 1 x x ts1 x 0 0 1 1 x x x ts0 x 0 1 0 1 x x x ref/comp o/p mode disabled to high state disabled to high state disabled to high state disabled to high state disabled to high state disabled to high state f ref switched f comp switched rts 0 1 1 1 1 1 0 1 re 0 0 0 0 0 0 1 1 test mode description normal operation charge pump sink, status byte fl = 1 charge pump source, status byte fl = 0 charge pump disabled, status byte fl = 0 port p0 = f pd /2 varactor drive output disabled normal operation normal operation c1 byte 5, bit 1 0 0 1 1 c0 byte 5, bit 2 0 1 0 1 min. + - 90 + - 195 +- 416 +- 900 current ( a) typ. + - 120 + - 260 +- 555 +- 1200 max. + - 150 +- 325 +- 694 + - 1500 table 7 - charge pump current 300 100 100 frequency (mhz) v in (mv rms into 50 ? ) operating window 1000 2000 3000 10 40 3500 300 100 100 frequency (mhz) v in (mv rms into 50 ? ) operating window 1000 2000 3000 10 40 3500 300 2700 figure 4a - prescaler disabled, pe = 0 figure 4b - prescaler enabled, pe = 1 figure 4 - typical input sensitivity
7 SP5659 preliminary information double conversion tuner systems the high 27ghz maximum operating frequency and excellent noise characteristics of the SP5659 allow the construction of double conversion high if tuners. a typical as shown in fig. 5 uses the SP5659 as the first local oscillator control for full band up conversion to an if of greater than 1ghz. the wide range of reference division ratios allows the SP5659 to be used for both the up converter local oscillator with a high phase comparison frequency (hence low phase noise) and the down converter which uses the device in a lower comparison frequency mode, which gives a fine step size. 50-900mhz sp8659 sp8659 sp8659 sp8659 reference clock first lo second lo 1650-2700mhz 1 6ghz 38 9mhz figure 5 - example of double conversion from vhf/uhf frequencies to tv if application notes an application note, an168, is available for designing with synthesisers such as the SP5659. it covers aspects such as loop filter design and decoupling. the application note is published in the zarlink semiconduc- tor media ic handbook. a generic test/demonstration board has been produced, which can be used for the SP5659. a circuit diagram and layout for the board are shown in figs. 7 and 8. the board can be used for the following purposes: (a) measuring rf sensitivity performance (b) indicating port function (c) synthesising a voltage controlled oscillator (d) testing external reference sources the programming codes relevant to these tests are given in fig. 3. bcw31 2 2n 47k 16k tuner SP5659 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1n 1 30v 22k 1n oscillator output 1 5v 10n adc p0 p1 1 12v 68p 13 3k 15n p3 p2 ref/comp 10n control micro ref address sda scl SP5659 1 2 3 4mhz 18p optional application using on-chip crystal controlled oscillator figure 6 - typical application
8 SP5659 preliminary information 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 5v c10 1n c4 1n c5 1n c3 68p r6 13 3k c2 15n tr1 2n3904 r8 16k r9 47k c12 2 2n p3 var gnd c7 100n c8 100n c9 100n 1 5v 1 30v 1 12v p2 r8 22k c13 100p c14 100p p1 disable/ref enable data/sda clock/scl c1 18p x1 4mhz external reference sk2 c6 10n (not fitted, see note 3) sk1 rf input notes 1. the circuit diagram shown is designed for use with a number of synthesisers. 2. the led connected to pin 11 is redundant when an SP5659 is used in this board. 3. to use an external reference, capacitor c6 must be fitted and capacitor c1 removed from the board. r3 4 7k d3 r2 4 7k d2 r1 4 7k d1 r4 4 7k d4 r5 4 7k d5 p4 1 12v c11 1n figure 7 - test board circuit diagram figure 8 - test board layout rjm51 bottom silk screen component location
9 SP5659 preliminary information loop bandwidth most applications for which the SP5659 is intended require a loop filter bandwidth of between 2khz and 10khz. typically, the vco phase noise will be specified at both 1khz and 10khz offset. it is common practice to arrange the loop filter bandwidth such that the 1khz figure lies within the loop bandwidth. the phase noise therefore depends on the synthesiser comparator noise floor rather than the vco the 10khz offset figure should depend on the vco provided that the loop has been designed correctly and is not underdamped. reference source the SP5659 offers optimal local oscillator phase noise performance when operated with a large step size. this is because the local oscillator phase noise within the loop bandwidth is: f lo phase comparator noise floor 1 20log 10 f comp where f lo is the local oscillator frequency and f comp is the phase comparator frequency. ?? ?? assuming the phase comparator noise floor is flat regardless of sampling frequency, this means that the best performance will be achieved when the overall local oscillator to phase comparator division ratio is a minimum. the are two ways of achieving a higher phase comparator sampling frequency: 1. reduce the division ratio between the reference source and the phase comparator 2. use a higher reference source frequency the second approach may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. driving two SP5659s from a common reference the ref/comp output on pin 3 allows two synthesisers to be driven from a common reference. to do this, the first device should be programmed by setting re = 1 and rts = 0. the driven device should be programmed for normal operation with re = 0 and rts = 0. the two devices should be connected as shown in fig. 9. figure 10 - typical rf input impedance s 11: z o = 50 ? normalised to 50 ? frequency markers at 100mhz, 500mhz, 1ghz and 2 7ghz j 2 j 1 j 0.5 j 0.2 0 2 j 0.2 2 j 0.5 2 j 1 2 j 2 1 0.5 0.2 j 5 2 j 5 2 5 SP5659 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4mhz 18p SP5659 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1n figure 9 - two SP5659 devices using a common reference
10 SP5659 preliminary information figure 11 - input/output interface circuits rf input 500 500 charge pump rf inputs loop amplifier reference oscillator address input sda, scl and adc ref/comp output v cc 3k 30k 10k address v cc v ref 100 drive output os (o/p disable) 200 scl / sda/adc 3k ack * * on sda onl y v cc cryst al v cc v cc port ref/comp enable/ disable output ports rf input 13 14 16 1 4 3 2
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. trading as zarlink semiconductor o r its subsidiaries (collectively zarlink ) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liabil ity otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either e xpress or implied, under patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of produc ts are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or o ther intellectual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide onl y and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. man ufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure t o perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink s conditions of sale which are available on request. purchase of zarlink s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2001, zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

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